1. Field of the Invention
The present invention relates generally to an electrical power supply and in particular to an apparatus and method for synchronizing switching frequencies of multiple power regulators.
2. Description of the Related Art
Power regulators are used in many electrical devices to provide controlled power to the circuits in the device. The power regulators may be used to translate the voltage to a desired level, to regulate the power to a particular output level, or the like. Power regulators are configured according to several different designs. One such design is a switching power regulator, where an input voltage is switched on and off rapidly and the resulting signal is smoothed to provide an output voltage at a lower level. In many systems, multiple regulators are used to provide multiple output voltages at different levels.
A power regulator 24 is shown generally in FIG. 1, including an input 10, a power conversion stage 12, and an output 14. The power conversion stage 12 has an output 16 that is fed through a feedback network 18 to an error amplifier 20 that in turn feeds a controller 22 which controls the power conversion stage 12.
The controller block 22 of the power regulator 24 is shown generally in FIG. 2, including an oscillator 28, a ramp generator 30, and a pulse width modulator 32. The oscillator 28 operating frequency is determined by a frequency setting component 34 that is typically external to the controller 22. The oscillator block 28 may, optionally, include a synchronization input (sync input) 36 that forces the oscillator operating frequency to match the frequency of the sync signal. In the absence of an external sync signal, the oscillator 28 runs at the frequency determined by its frequency setting component 34. This frequency is commonly called the “free running frequency”.
The principal function of the oscillator 28 is to provide the timing signals to generate a ramp signal, such as generated by the ramp generator 30, that is a required input to a pulse width modulator, such as the pulse width modulator 32. The ramp signal is generally a saw-tooth shape with a linear rise to a peak value and an abrupt decrease back to a minimum value. The frequency of the ramp signal is equal to the frequency of the oscillator output. The period of one cycle of the ramp waveform, T, is equal to 1/fosc, where fosc is the oscillator operating frequency.
In many systems, multiple power regulators are used. Due to manufacturing tolerances, otherwise identical regulators operate at slightly different free running frequencies. The ramp waveforms of three regulators operating at slightly different frequencies are shown in a graph 40 in FIG. 3. The graph 40 is actually several graphs positioned above one another so as to facilitate comparison of timing of the illustrated signals. The horizontal axis represents common time for all the signals and the vertical axis indicates voltage level for each signal but the voltage levels are not common as between the signals and instead are shifted vertically with respect to one another.
In FIG. 3, a Ramp 1 signal, referenced 42, is from the lowest frequency oscillator and has a waveform duration period designated as TSLOW. A Ramp 2 signal, referenced 44, is from an oscillator running at a desired nominal frequency. The period of the Ramp 2 signal 44 is designated by TNOM. The Ramp 3 signal 46 is from the highest frequency oscillator. The period of the Ramp 3 signal 46 is designated by TFAST. As shown, these three waveforms 42, 44 and 46 represent three regulators that are running asynchronously. In particular, the periods of the three signals are compared and shown to differ in duration as indicated by the arrows. The switching frequencies of these three regulators are unrelated.
In systems with multiple switching regulators running asynchronously, undesirable beat frequencies are generated that occur at the sum and difference frequencies of the multiple oscillator frequencies. These beat frequencies represent undesirable noise that is injected in to the electrical system. In an effort to eliminate the generation of beat frequencies, some regulators support the option of synchronizing their oscillators to an external synchronization signal. This forces all regulators to run at the same frequency.
One known method of synchronization of oscillators exhibits some undesirable restrictions and side effects. These side effects are illustrated in the graph 48 of FIG. 4. In FIG. 4 is shown a common horizontal time axis for four signals and a vertical axis that is not common for the four signals but instead has been shifted to permit comparison of the signals. The same three regulator signals shown in FIG. 3 are now supplied a synchronization signal labeled Sync Pulse and referenced 50. The period of the Sync Pulse signal 50 is equal to TNOM, the same as the period of the Ramp 2 signal 44. In most synchronization circuits, the rising edge of the sync signal causes the ramp signal to immediately return to its minimum value and begin a new rising interval. In FIG. 4, the Ramp 1 signal 42, which represents the lowest free running operating frequency, behaves as expected. When a sync pulse 52 occurs in the sync pulse signal 50, the current ramp is terminated and the next cycle begins. The period of the Ramp 1 signal 42 is now equal to the period of the Sync Pulse signal 50. In similar fashion, the Ramp 2 signal 44, which represents the nominal free running frequency, is also locked to the Sync Pulse period TNOM. The Ramp 3 signal 46a, which represents the highest free running frequency, exhibits an unusual behavior, however. Since it is running at a higher frequency than the Sync Pulse signal 50, its oscillator completes its normal ramp cycle and starts another cycle before the next pulse 52 of the Sync Pulse signal 50 arrives. When the pulse 52 of the Sync Pulse signal 50 arrives at the oscillator of the Ramp 3 signal 46a, it causes a termination of the ramp cycle that is in progress and forces a new ramp cycle to start. This produces a corrupted ramp waveform as shown at 46a that will cause improper operation of the pulse width modulator 32. To resolve this issue, the known circuits require that the frequency of the synchronizing signal must be equal to or higher than the highest free running frequency of the oscillators to be synchronized. This is an undesirable restriction that can cause other adverse side effects.